
`include "common_header.verilog"

//  *************************************************************************
//  File : mtip_dffvec_ena
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2009 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Daniel Koehler
//  info@morethanip.com
//  *************************************************************************
//  Description : Configurable width vector for pipeline usage
//  Version     : $Id: mtip_dffvec_ena.v,v 1.1.1.1 2011/05/13 07:47:11 dk Exp $
//  *************************************************************************

module mtip_dffvec_ena (
   reset,
   clk,
   ena,
   i,
   o);

parameter NWIDTH = 8;           // width of vector

input   reset;                  //  output clock domain
input   clk;                    //  output clock to synchronize to
input   ena;                    //  clock enable
input   [NWIDTH - 1:0] i;       //  input data
output  [NWIDTH - 1:0] o;       //  output data one cycle later

reg     [NWIDTH - 1:0] o;

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      o <= {(NWIDTH){1'b 0}};
      end
   else
      begin
      if (ena == 1'b 1)
         begin
         o <= i;
         end
      end
   end

endmodule // module mtip_dffvec_ena
